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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
D D D D D D D
Hot Plug Protection 0.6 to 1.5 Gigabits Per Second (Gbps) Serializer/Deserializer High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD) 2.5 V Power Supply for Low Power Operation Programmable Voltage Output Swing on Serial Output Interfaces to Backplane, Copper Cables, or Optical Converters Rated for Industrial Temperature Range
D D D D D D
On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization On-Chip PLL Provides Clock Synthesis From Low-Speed Reference Receiver Differential Input Thresholds 200 mV Minimum Typical Power: 250 mW Loss of Signal (LOS) Detection Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link
description
The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency). The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000 - 2003, Texas Instruments Incorporated
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
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description (continued)
The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface. The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state. The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock. To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501. The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data. The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from - 40C to 85C.
AVAILABLE OPTIONS PACKAGE TA PowerPAD QUAD FLATPACK (PQFP) TLK1501IRCP TLK1501IRCPR
- 40C to 85C
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RCP PACKAGE (TOP VIEW)
TXD2 TXD1 TXD0 GNDA DOUTTXP DOUTTXN GNDA VDDA RREF VDDA DINRXP DINRXN GNDA RXD0 VDD TXD3 TXD4 TXD5 GND TXD6 TXD7 GTX_CLK VDD TXD8 TXD9 TXD10 GND TXD11 TXD12 TXD13
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
RXD1 RXD2 VDD RXD3 RXD4 RXD5 RXD6 GND RXD7 RX_CLK RXD8 RXD9 VDD RXD10 RXD11 RXD12 RXD13 GND
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TXD14 GND TXD15 TX_EN LOOPEN TX_ER V DD ENABLE LCKREFN PRBSEN TESTEN GND RX_ER/PRBS_PASS RX_DV/LOS RXD15 RXD14
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block diagram
LOOPEN PRBSEN TX_EN TX_ER PRBS Generator 10 DOUTTXP DOUTTXN 2:1 10 MUX 8B/10B Encoder Parallel to Serial BIAS RREF
PRBSEN
8 TD(0-15) 16 Bit Register
10 MUX
10 Bit Clock
8
8B/10B Encoder
10
GTX_CLK TESTEN ENABLE PRBSEN Controls: PLL,Bias,Rx, Tx
Multiplying Clock Synthesizer Bit Clock
RX_ER PRBS_PASS
2:1 MUX PRBSEN
Interpolator and Clock Recovery
2:1 MUX
RX_CLK RX_DV/LOS
PRBS Verification
Recovered Clock
8 16 Bit Register RD(0-15)
Comma Detect and 8B/10B Decoding Comma Detect and 8B/10B Decoding
10 1:2 MUX 10 10 Serial to Parallel 2:1 Data MUX
DINRXP DINRXN
8
Signal Detect (LOS)
Figure 1. TLK1501 Block Diagram
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Terminal Functions
TERMINAL NAME DINRXN DINRXP DOUTTXN DOUTTXP NO. 53 54 59 60 TYPE I O DESCRIPTION Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a copper or an optical I/F module. Serial transmit outputs (Hi-Z on power up). DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. During power-on reset these terminals are high impedance. Device enable (w/pullup). When this terminal is held low, the device is placed in power-down mode. Only the signal detect circuit on the serial receive pair is active. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation. Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
ENABLE
24
I
GND
5, 13, 18, 28, 33, 43 52, 58, 61 8 I
GNDA GTX_CLK
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX. Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter interface signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 30 MHz to 75 MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization. Lock to reference (w/pullup). When LCKREFN is low, the receiver clock is frequency locked to GTX_CLK. This places the device in a transmit only mode since the receiver is not tracking the data. When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS are in a high-impedance state. When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive valid codes from the synchronization state machine before the transmitter is enabled.
LCKREFN
25
I
LOOPEN
21
I
Loop enable (w/pulldown). When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active. PRBS test enable (w/pulldown). When asserted high results of pseudorandom bit stream (PRBS) tests can be monitored on the RX_ER/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid PRBS is being received. Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other side of the resistor is connected to analog VDD. The resistor is used to provide an accurate current reference to the transmitter circuitry. Receive data bus (Hi-Z on power up). These outputs carry 16-bit parallel data output from the transceiver to the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 13. These terminals are in high-impedance state during power-on reset.
PRBSEN
26
I
RREF
56
I
RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15
51 50 49 47 46 45 44 42 40 39 37 36 35 34 32 31
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Terminal Functions (Continued)
TERMINAL NAME RX_CLK NO. 41 TYPE O DESCRIPTION Recovered clock (low on power up). Output clock that is synchronized to RXD, RX_ER, RX_DV/LOS. RX_CLK is the recovered serial data rate clock divided by 20. RX_CLK is held low during power-on reset. Receive error (Hi-Z on power up). When RX_ER and RX_DV/LOS are asserted, indicates that an error was detected somewhere in the frame presently being output on the receive data bus. When RX_ER is asserted and RX_DV/LOS is deasserted, indicates that carrier extension data is being presented. RX_ER is in high-impedance state during power-on reset. When PRBSEN= low (deasserted), this terminal is used to indicate receive error (RX_ER). When PRBSEN = high (asserted), this terminal indicates status of the PRBS test results (High=pass). RX_DV/ LOS 30 O Receive data valid (Hi-Z on power up). RX_DV/LOS is output by the transceiver to indicate that recovered and decoded data is being output on the receive data bus. RX_DV/LOS is asserted low continuously from the first recovered word of the frame through the final recovered word and is negated prior to the first rising edge of RX_CLK that follows the final word. RX_DV/LOS is in high-impedance state during power-on reset. If, during normal operation, the differential signal amplitude on the serial receive terminals drops significantly below 200 mV, RX_DV/LOS is asserted high along with RX_ER and the receive data bus to indicate a loss of signal condition. If the device is in power-down mode, RX_DV/LOS is the output of the signal detect circuit and is asserted low when a loss of signal condition is detected. TESTEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 TXD8 TXD9 TXD10 TXD11 TXD12 TXD13 TXD14 TXD15 TX_EN 27 62 63 64 2 3 4 6 7 10 11 12 14 15 16 17 19 20 I I Test mode enable (w/pulldown). This terminal should be left unconnected or tied low. Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the transceiver on the rising edge of GTX_CLK as shown in Figure 10.
RX_ER/ PRBS_PASS
29
O
I
Transmit enable (w/pulldown). TX_EN in combination with TX_ER indicates the protocol device is presenting data on the transmit data bus for transmission. TX_EN must be asserted high with the first word of the preamble and remain asserted while all words to be transmitted are presented on the transmit data bus(TXD). TX_EN must be negated prior to the first rising edge of GTX_CLK following the final word of a frame. Transmit error coding (w/pulldown). When TX_ER and TX_EN are high, indicates that the transceiver generates an error somewhere in the frame presently being transferred. When TX_ER is asserted and TX_EN is deasserted, indicates the protocol device is presenting carrier extension data. When TX_ER is deasserted with TX_EN asserted, indicates that normal data is being presented. Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
TX_ER
22
I
VDD
1, 9, 23, 38, 48 55, 57
VDDA
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter
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detailed description
transmit interface The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the GTX_CLK. The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times, creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data is transmitted LSB (TXD0) first. The transmitter also inserts commas at the beginning of the transmission for byte synchronization. transmit data bus The transmit bus interface accepts 16-bit single-ended TTL parallel data at the TXD[0:15] terminals. Data is valid on the rising edge of the GTX_CLK when the TX_EN is asserted high and the TX_ER is deasserted low. The GTX_CLK is used as the word clock. The data, enable, and clock signals must be properly aligned as shown in Figure 2. Detailed timing information can be found in the electrical characteristics table.
GTX_CLK
TXDn, TX_EN, TX_ER tsu th
Figure 2. Transmit Timing Waveform
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detailed description (continued)
transmission latency The data transmission latency of the TLK1501 is defined as the delay from the initial 16-bit word load to the serial transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly. The minimum transmit latency (Tlatency ) is 34 bit times; the maximum is 38 bit times. Figure 3 illustrates the timing relationship between the transmit data bus, the GTX_CLK and serial transmit terminals.
Transmitted 20-Bit Word DOUTTXP, DOUTTXN (Tlatency) TXD[0-15] 16-Bit Word to Transmit
GTX_CLK Non-Jedec symbol
Figure 3. Transmitter Latency 8-bit/10-bit encoder All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking. The TLK1501 uses the 8-bit/10-bit encoding algorithm that is used by the fibre channel and the gigabit ethernet. This is transparent to the user, as the TLK1501 internally encodes and decodes the data such that the user reads and writes actual 16-bit data. The 8-bit/10-bit encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve its transmission characteristics. Since the TLK1501 is a 16-bit wide interface, the data is split into two 8-bit wide bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependant upon two additional input signals, the TX_EN and TX_ER. When the TX_EN is asserted and the TX_ER deasserted, then the data bits TXD[0:15] are encoded and transmitted normally. When the TX_EN is deasserted, and TX_ER is asserted, then the encoder generates a carrier extend consisting of two K23.7 (F7F7) codes. If the TX_EN and the TX_ER are both asserted, then the encoder generates a K30.7 (FEFE) code. Table 1 provides the transmit data control decoding. Since the data is transmitted in 20-bit serial words, K codes indicating carrier extend and transmit error propagation are transmitted as two 10-bit K-codes. Table 1. Transmit Data Controls
TX_EN 0 0 1 1 TX_ER 0 1 0 1 ENCODED 20 BIT OUTPUT IDLE (< K28.5, D5.6 > or < K28.5, D16.2 >) Carrier extend (K23.7, K23.7) Normal data character Transmit error propagation (K30.7, K30.7)
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detailed description (continued)
IDLE insertion The encoder inserts the IDLE character set when no payload data is available to be sent. IDLE consists of a K28.5 (BC) code and either a D5.6 (C5) or a D16.2 (50) character. The K28.5 character is defined by IEEE802.3z as a pattern consisting of 0011111010 ( a negative number beginning disparity) with the 7 MSBs (0011111), referred to as the comma character. Since data is transmitted to the TLK1501 20 in a GTX_CLK cycle. The comma character is converted to two 10-bit wide code. PRBS generator The TLK1501 has a built-in 27-1 PRBS (pseudorandom bit stream) function. When the PRBSEN terminal is forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a BERT (bit error rate tester), the receiver of another TLK1501, or can be looped back to the receive input. Since the PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors by a BERT. parallel-to-serial The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally generated bit clock, which is 10 times the GTX_CLK input frequency. The LSB (TXD0) is transmitted first. high-speed data output The high-speed data output driver consists of a current-mode logic (CML) differential pair that can be optimized for a particular transmission line impedance and length. The line can be directly-coupled or ac-coupled. Refer to Figure 15 and Figure 16 for termination details.
receive interface
The receiver portion of the TLK1501 accepts 8-bit/10-bit encoded differential serial data. The interpolator and clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock. receive data bus The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data is valid on the rising edge of the RX_CLK when the RX_DV/LOS is asserted high and the RX_ER is deasserted low. The RX_CLK is used as the recovered word clock. The data, enable, and clock signals are aligned as shown in Figure 4. Detailed timing information can be found in the switching characteristics table.
RX_CLK
RXDn, RX_DV, RX_ER tsu th
Figure 4. Receive Timing Waveform
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detailed description (continued)
data reception latency The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RXD0 received as first bit. The receive latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly. The minimum receive latency (Rlatency) is 76 bit times; the maximum is 107 bit times. Figure 5 illustrates the timing relationship between the serial receive terminals, the recovered word clock (RX_CLK), and the receive data bus.
20-Bit Encoded Word DINTXP, DINTXN (Rlatency) RXD[0-15] 16-Bit Decoded Word
RX_CLK Non-Jedec symbol
Figure 5. Receiver Latency serial-to-parallel Serial data is received on the DINRXP and DINRXN terminals. The interpolator and clock recovery circuit locks to the data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders where the data is then synchronized to the incoming data steam word boundary by detection of the K28.5 synchronization pattern. comma detect and 8-bit/10-bit decoding The TLK1501 has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded data (half of the 20 bit received word) back into 8-bits. The comma detect circuit is designed to provide for byte synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data. When the serial data is received and converted to parallel format again, a way is needed to recognize the byte boundary. Usually this is accomplished through the use of a synchronization pattern. This is usually a unique pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is used by the comma detect circuit on the TLK1501 to align the received serial data back to its original byte boundary. The decoder detects the K28.5 comma, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding. It then converts the data back into 8-bit data, removing the control words. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel data clock (RX_CLK) and the output is valid on the rising edge of the RX_CLK. It is possible for a single bit error in a data pattern to be interpreted as comma on an erroneous boundary. If the erroneous comma is taken as the new byte boundary, all subsequent data is improperly decoded until a property aligned comma is detected. To prevent a data bit error from causing a valid data packet to be interpreted as a comma and thus cause the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after receiving a properly aligned comma after the link is established. The link is established after three idle patterns or one valid data pattern is properly received. The comma alignment circuit is re-enabled when the synchronization state machine detects a loss of synchronization condition (see synchronization and initialization).
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comma detect and 8-bit/10-bit decoding (continued) Two output signals, RX_DV/LOS and RX_ER, are generated along with the decoded 16-bit data output on the RXD[0:15] terminals. The output status signals are asserted as shown in Table 2. When the TLK1501 decodes normal data and outputs the data on RXD[0:15], RX_DV/LOS is asserted (logic high) and RX_ER is deasserted (logic low). When the TLK1501 decodes a K23.7 code (F7F7) indicating carrier extend, RX_DV/LOS is deasserted and RX_ER is asserted. If the decoded data is not a valid 8-bit/10-bit code, an error is reported by the assertion of both RX_DV/LOS and RX_ER. If the error was due to an error propagation code, the RXD bits output hex FEFE. If the error was due to an invalid pattern, the data output on RXD is undefined. When the TLK1501 decodes an IDLE code, both RX_DV/LOS and RX_ER are deasserted and a K28.5 (BC) code followed by either a D5.6 (C5) or D16.2 (50) code are output on the RXD terminals. Table 2. Receive Status Signals
RECEIVED 20 BIT DATA IDLE (< K28.5, D5.6 >, < K28.5, D16.2 >) Carrier extend (K23.7, K23.7) Normal data character (DX.Y) Receive error propagation (K30.7, K30.7) RX_DV/LOS 0 0 1 1 RX_ER 0 1 0 1
loss of signal detection The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. The TLK1501 reports this condition by asserting, the RX_DV/LOS, RX_ER and RXD[0:15] all to a high state. As long as the signal is above 200 mV in differential magnitude, the LOS circuit does not signal an error condition. power down mode When the ENABLE pin is deasserted low, the TLK1501 will go into a power down mode. In the power down mode, the serial transmit pins (DOUTTXP, DOUTTXN), the receive data bus pins (RXD[0:15]), and RX_ER will go into a high-impedance state. In the power-down mode the RX_DV/LOS pin acts as an output of the signal detection circuit which remains active. If the signal detection circuit detects a valid differential signal amplitude of >200 mV on each of the serial receive pins (DINRXP, DINRXN), RX_DV/LOS is driven high. If no signal of sufficient amplitude is detected, the signal detection circuit will indicate a loss of signal by driving RX_DV/LOS low. In the power-down condition, the signal detection circuit draws less than 5 mW. synchronization and initialization The TLK1501 has a synchronization-state machine which is responsible for handling link initialization and synchronization. Upon power up or reset, the state machine enters the acquisition (ACQ) state and searches for IDLE. Upon receiving three consecutive IDLEs or carrier extends, the state machine enters the synchronization (SYNC) state. If, during the acquisition process, the state machine receives valid data or an error propagation code, it immediately transitions to the SYNC state. The SYNC state is the state for normal device transmission and reception. The initialization and synchronization state diagram is provided in Figure 6.
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synchronization and initialization (continued)
Invalid Code Word Received
Power-Up/Reset
ACQ (Link Acquisition) 3 Consecutive Valid IDLEs or Carrier Extends, or 1 Valid Data or Error Propagation Loss of Link Link Established Valid Code Word Received 1 Invalid Code Word Received Link in Question Link Re-established 4 Consecutive Valid Code Words Received
3 Invalid Code Words Received
CHECK (Look for Valid Code)
SYNC (Normal Operation)
Figure 6. Initialization and Synchronization State Diagram If during normal transmission and reception, an invalid code is received, the TLK1501 notifies the attached system or protocol device as described in comma detect and 8-bit/10-bit decoding. The synchronization state machine transitions to the CHECK state. The CHECK state determines whether the invalid code received was caused by a spurious event or a loss of the link. If, in the CHECK state, the decoder sees four consecutive valid codes, the state machine determines the link is good and transitions back to the SYNC state for normal operation. If, in the CHECK state, the decoder sees three invalid codes (not required to be consecutive), the TLK1501 determines a loss of the link has occurred and transitions the synchronization-state machine back to the link-acquisition state (ACQ). The state of the transmit data bus, control terminals, and serial outputs during the link acquisition process is illustrated in Figure 7.
ACQ SYNC
TX_EN
xx
xx
xx
xx
xx xx
xx
TX_ER
xx
xx
xx
xx xx
xx
xx
TXD[0-15] DOUTTXP, DOUTTXN
xx
xx
xx
xx
xx xx
xx
xx
D0-D15
IDLE
D0-D15
Ca. Ext.
Error
Figure 7. Transmit Side Timing Diagram
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
synchronization and initialization (continued) The state of the receive data bus, status terminals, and serial inputs during the link acquisition process is illustrated in Figure 8 and Figure 9.
ACQ DINRXP, DINRXN
IDLE or Carrier Extend IDLE or Carrier Extend IDLE or Carrier Extend
SYNC D0-D15
RXD(0-15)
XXXXXXXXXXXXXXXXXXX
IDLE or Carrier Extend
IDLE or Carrier Extend
D0-D15
RX_ER
RX_DV,
RESET (Internal Signal)
Figure 8. Receive Side Timing Diagram (Idle or Carrier Extend)
ACQ DINRXP, DINRXN IDLE
Valid Data or Error Prop
SYNC D0-D15 D0-D15
RXD(0-15)
XXXXXXXXXXXXXXXXXXX
Valid Data or Error Prop
D0-D15
D0-D15
RX_ER
RX_DV
RESET (Internal Signal)
Figure 9. Receive Side Timing Diagram (Valid Data or Error Propagation) redundant port operation The TLK1501 allows users to design a redundant port by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, the RXD[0:15], RX_CLK and RX_ER, and RX_DV/LOS to go to a high-impedance state. PRBS verification The TLK1501 also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can check for errors and report the errors by forcing the RX_ER/PRBSPASS terminal low.
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EEEE EEEE
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
reference clock input The reference clock (GTX_CLK) is an external input clock that synchronizes the transmitter interface. The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data on both its rising and falling edge, providing a serial data rate that is 20 times the reference clock. operating frequency range The TLK1501 is optimized for operation at a serial data rate of 1.2 Gbps. The TLK1501 may operate at a serial data rate between 0.6 Gbps to 1.5 Gbps. The GTX_CLK must be within 100 PPM of the desired parallel data rate clock. testability The TLK1501 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled so that an quiescent current test can be performed. The PRBS function allows for a BIST (built-in self-test). loopback testing The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling this terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loopback testing.) built-in self-test (BIST) The TLK1501 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry running at full speed can be realized. The successful completion of the BIST is reported on the RX_ER/PRBS_PASS terminal. power-on reset Upon application of minimum valid power, the TLK1501 generates a power-on reset. During the power-on reset the RXD, RX_ER, and RX_DV/LOS signal terminals to go to a high-impedance state. The RX_CLK is held low. The length of the power-on reset cycle is dependent upon the REFCLK frequency, but is less than 1 ms.
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POST OFFICE BOX 655303
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to 3 V Voltage range at TXD, ENABLE, GTX_CLK, TX_EN, TX_ER, LOOPEN, PRBS_PASS . . . . . . . . . . - 0.3 to 4 V Voltage range at any other terminal except above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 to VDD+0.3 V Package power dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM:3 KV, CDM:1.5 KV Characterized free-air operating temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 85C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground. DISSIPATION RATING TABLE PACKAGE RCP64 RCP64 RCP64# TA 2 5_C POWER RATING 5.25 W 3.17 W 2.01 W DERATING FACTOR ABOVE TA = 25_C 46.58 mW/_C 23.70 mW/_C 13.19 mW/_C TA = 70_C POWER RATING 2.89 W 1.74 W 1.11 W
This is the inverse of the traditional junction-to-ambient thermal resistance (RJA). 2 oz. Trace and copper pad with solder. 2 oz. Trace and copper pad without solder. # Standard JEDEC High-K board.
For more information, refer to TI application note PowerPAD Thermally Enhanced Package, TI literature number SLMA002.
electrical characteristics over recommended operating conditions
PARAMETER Supply voltage, VDD Supply current, ICC current VDD = 2.5 V, Frequency = 0.6 Gbps, PRBS pattern VDD = 2.5 V, Frequency = 1.5 Gbps, PRBS pattern VDD = 2.5 V, Frequency = 0.6 Gbps, PRBS pattern VDD = 2.5 V, Frequency = 1.5 Gbps, PRBS pattern VDD = 2.5 V, Frequency = 1.5 Gbps, worst case pattern|| Shutdown current PLL startup lock time Data acquisition time Operating free-air temperature, TA || Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver. -40 Enable = 0, VDDA + VDD terminals = max VDD,VDDA = 2.3V, EN to PLL acquire 2 0.1 1024 85 0.4 TEST CONDITIONS MIN 2.3 NOM 2.5 70 100 175 250 350 MAX 2.7 UNIT V mA mW mW mW mA ms bits C
Power dissipation, PD
reference clock (GTX_CLK) timing requirements over recommended operating conditions (unless otherwise noted)
PARAMETER Frequency Frequency Frequency tolerance Duty cycle Jitter Peak-to-peak TEST CONDITIONS Minimum data rate Maximum data rate MIN Typ -0.01% Typ -0.01% - 100 40% 50% 60% 40 ps TYP 30 75 MAX Typ+0.01% Typ+0.01% UNIT MHz MHz ppm
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
TTL input electrical characteristics over recommended operating conditions (unless otherwise noted), TTL signals: TXDO-TXD15, GTX_CLK, LOOPEN, LCKREFN, PRBS_EN
PARAMETER VIH VIL IIH IIL CI tr tf tsu th Rise time, GTX_CLK, TX_EN, TX_ER, TXD Fall time, GTX_CLK, TX_EN, TX_ER, TXD TXD, TX_EN, TX_ER setup to GTX_CLK TXD, TX_EN, TX_ER hold to GTX_CLK High-level input voltage Low-level input voltage Input high current Input low current TEST CONDITIONS See Figure 10 See Figure 10 VDD = MAX, VIN = 2 V VDD = MAX, VIN = 0.4 V 0.8 V to 2 V 0.8 V to 2 V, C = 5 pF, See Figure 10 2 V to 0.8 V, C = 5 pF, See Figure 10 See Figure 10 See Figure 10 1.5 0.4 1 1 - 40 4 MIN 1.7 NOM MAX 3.6 0.80 40 UNIT V V A A pF ns ns ns ns
3.6 V 2.0 V GTX_CLK 0.8 V 0V tr tf 3.6 V TX_ER, TX_EN, TXD[0-15] 2.0 V 0.8 V 0V tsu tf th tr
Figure 10. TTL Data Input Valid Levels for ac Measurements
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
TTL output switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VOH VOL tr(slew) tf(slew) High-level output voltage Low-level output voltage Slew rate (rising), magnitude of RX_CLK, RX_ER, RX_DV/LOS, RXD Slew rate (falling), magnitude of RX_CLK, RX_ER, RX_DV/LOS, RXD TEST CONDITIONS IOH = -1 mA, VDD = MIN IOL = 1 mA, VDD = MIN 0.8 V to 2 V,, C = 5 pF, See Figure 11 0.8 V to 2 V, C = 5 pF, See Figure 11 50% voltage swing, GTX_CLK =30 MHz, See Figure 11 50% voltage swing, GTX_CLK = 75 MHz, See Figure 11 50% voltage swing, GTX_CLK = 30 MHz, See Figure 11 50% voltage swing, GTX_CLK = 75 MHz, See Figure 11 MIN 2.10 GND 0.5 0.5 15 5.5 15 5.5 NOM 2.3 0.25 0.5 MAX UNIT V V V/ns V/ns ns ns ns ns
tsu
RXD RX_DV/LOS, RX_ER setup to RX_CLK RX CLK RXD, RX DV/LOS RX ER
th
RXD RX_DV/LOS, RX_ER hold to RX_CLK RX CLK RXD, RX DV/LOS RX ER
2.7 V 2.0 V RX_CLK 0.8 V 0V tr(slew) tf(slew) 2.7 V RX_DV, RX_ER, RXD[0-15] 2.0 V 0.8 V 0V tsu tf(slew) th tr(slew)
Figure 11. TTL Data Output Valid Levels for ac Measurements
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
transmitter/receiver characteristics
PARAMETER VOD(p) VOD(pp_p) VOD(d) VOD(pp_d) V(term) (t ) VID V(cmr) Ilkg Ci Preemphasis VOD, direct, VOD(p) = |VTXP - VTXN| Differential, peak-to-peak output voltage with preemphasis Deemphais output voltage, |VTXP - VTXN| Differential, peak-to-peak output voltage with de-emphasis Transmit termination voltage range range, Receiver input voltage differential, |VRXP - VRXN| Receiver common mode voltage range, (VRXP + VRXN)/2 Receiver input leakage current Receiver input capacitance Differential output jitter at 1.5 Gbps, Random + deterministic, PRBS pattern Serial data total jitter (peak-to-peak) ( eak-to- eak) Differential output jitter at 0.6 Gbps, Random + deterministic, PRBS pattern RL = 50 , CL = 5 pF, See Figure 12 Differential input jitter, random + determinisitc, PRBS pattern at zero crossing See Figure 2 See Figure 5 100 0.10 0.10 150 Rt = 50 , dc-coupled, See Figure 15 Rt = 50 , dc-coupled, See Figure 15 1500 200 1500 -10 VDD - VID/2 10 2 Rt = 50 , RREF = 200 , dc-coupled, See Figure 12 TEST CONDITIONS MIN 840 1680 760 1520 TYP 1050 2100 950 1900 MAX 1260 2520 1140 2280 UNIT mV mVp-p mV mVp-p mV mV mV mV A pF UI UI ps
VDD VDD - VID/2
tt, tf
Differential output signal rise, fall time (20% to 80%) Jitter tolerance
0.60 34 76 38 107
UI bits bits
td(Tx latency) Tx latency td(Rx latency) Rx latency UI is the time interval of one serialized bit. VOD(p)
VOD(d)
V(term) tf tr VOD(d) Bit Time Bit Time VOD(p)
VOD(pp_d) VOD(pp_p)
Figure 12. Differential and Common-Mode Output Voltage Definitions
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
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THERMAL INFORMATION
PARAMETER TEST CONDITION Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land RJA Junction-to-free-air thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land Board-mounted, no air flow, JEDEC test board Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land RJC Junction-to-case thermal resistance Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land Board-mounted, no air flow, JEDEC test board MIN TYP 21.47 C/W MAX UNIT
42.20 75.83 0.38
0.38 7.8
C/W
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
APPLICATION INFORMATION
VDDA 1 nF - 10 nF 1 nF - 10 nF Rt VDD Recommended use of 0.01 F Capacitor per VDD terminal 5 at 100 MHz 200 TXD2 TXD1 TXD0 0.01 F 0.01 F 0.01 F Vt 810 Rt 1 nF - 10 nF Rt
Vt 1 nF - 10 nF Rt
0.01 F 0.01 F
RREF
DOUTTXP
GNDA V DDA
RREF V DDA
DOUTTXN
DINRXP
DINRXN
GNDA
GNDA
VDD TXD3 TXD4 TXD5 GND TXD6 TXD7 GTX_CLK VDD TXD8 TXD9 TXD10 GND TXD11 TXD12 TXD13
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
RXD1 RXD2 VDD RXD3 RXD4 RXD5 RXD6 GND RXD7 RX_CLK RXD8 RXD9 VDD RXD10 RXD11 RXD12 RXD13 GND RXD15 RXD14
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND TXD15 TX_EN TXD14 LCKREFN RX_ER/PRBS_PASS RX_DV/LOS TX_ER V DD ENABLE LOOPEN PRBSEN TESTEN GND
Figure 13. External Component Interconnection
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RXD0
TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
APPLICATION INFORMATION recommended values of external resistors (1% tolerance)
PARAMETER R(t), Termination resistor R(REF), Reference resistor TEST CONDITIONS 50 environment 75 environment 50 environment 75 environment RECOMMENDED 50 75 200 300 UNIT
VOLTAGE vs RESISTOR REFERENCE
2.00 1.80 VODD at 75 1.60 VODP or VODD - V VODP at 75 1.40 1.20 1.00 0.80 0.60 100.00 VODD at 50 VODP at 50
150.00
200.00
250.00
300.00
RREF - Resistor Reference -
Figure 14. Differential Transmitter Voltage
choosing RREF resistor values
TLK1501 offers the flexibility to customize the voltage swing and transmission line termination by adjusting the reference resistor, RREF, and termination resistor, Rt. By choosing particular resistor values, the system can be optimized for a particular transmission line impedance, length, and controlling the output swing for EMI and attenuation concerns. Refer to Figure 14 to determine the nominal voltage swing and driver current as a function of resistor values. It is recommended that 1% tolerance resistors be used. Refer to Figure 15 for high-speed I/O directly coupled mode and Figure 16 for high-speed I/O ac-coupled mode.
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
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APPLICATION INFORMATION
V(term) Rt
TXP Transmission Line TXN
RXP + _ RXN
Transmission Line Rt Data Data V(term)
V(term) = VDD
Preemphasis = 21 mA (See Note A) De-Emphasis = 19 mA
TRANSMITTER
MEDIA
RECEIVER
NOTE A: This assumes RREF = 200 and termination resistance = 50 . See Figure 14 and section choosing RREF resistor values for more information.
Figure 15. High-Speed I/O Directly-Coupled Mode
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POST OFFICE BOX 655303
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
APPLICATION INFORMATION
VDD Rt TXP VDD Rt Transmission Line TXN 0.01 F Transmission Data Data Line VDD 200 V(term) 820 Rt 0.01 F V(term) RXN Rt V(term)
RXP + _
Preemphasis = 21 mA (See Note A) De-Emphasis = 19 mA
TRANSMITTER
MEDIA
RECEIVER
NOTE A: This assumes RREF = 200 and termination resistance = 50 . See Figure 14 and section choosing RREF resistor values for more information.
Figure 16. High-Speed I/O AC-Coupled Mode
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TLK1501 0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428E - JUNE 2000 - REVISED JULY 2003
APPLICATION INFORMATION designing with PowerPAD
The TLK1501 is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD to connection etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keep-out area for the 64-pin PFP PowerPAD package is 8 mm X 8 mm. It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction. Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI Web pages beginning at URL: http://www.ti.com.
Figure 17. Example of a Thermal Land For the TLK1501, this thermal land should be grounded to the low-impedance ground plane of the device. This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land. The land size should be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques. While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout, TI literature number SLLA020.
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